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NXP Semiconductors /LPC408x_7x /TIMER0 /MCR

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Interpret as MCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INTERRUPT_IS_DISABLE)MR0I 0 (FEATURE_DISABLED_)MR0R 0 (FEATURE_DISABLED_)MR0S 0 (INTERRUPT_IS_DISABLE)MR1I 0 (FEATURE_DISABLED_)MR1R 0 (FEATURE_DISABLED_)MR1S 0 (INTERRUPT_IS_DISABLE)MR2I 0 (FEATURE_DISABLED_)MR2R 0 (FEATURE_DISABLED_)MR2S 0 (THIS_INTERRUPT_IS_DI)MR3I 0 (FEATURE_DISABLED_)MR3R 0 (FEATURE_DISABLED_)MR3S 0RESERVED

MR0S=FEATURE_DISABLED_, MR3S=FEATURE_DISABLED_, MR3I=THIS_INTERRUPT_IS_DI, MR3R=FEATURE_DISABLED_, MR1I=INTERRUPT_IS_DISABLE, MR0R=FEATURE_DISABLED_, MR0I=INTERRUPT_IS_DISABLE, MR1S=FEATURE_DISABLED_, MR2S=FEATURE_DISABLED_, MR2I=INTERRUPT_IS_DISABLE, MR1R=FEATURE_DISABLED_, MR2R=FEATURE_DISABLED_

Description

Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

Fields

MR0I

Interrupt on MR0

0 (INTERRUPT_IS_DISABLE): Interrupt is disabled

1 (INTERRUPT_IS_GENERAT): Interrupt is generated when MR0 matches the value in the TC.
MR0R

Reset on MR0

0 (FEATURE_DISABLED_): Feature disabled.

1 (TC_WILL_BE_RESET_IF_): TC will be reset if MR0 matches it.
MR0S

Stop on MR0

0 (FEATURE_DISABLED_): Feature disabled.

1 (TC_AND_PC_WILL_BE_ST): TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
MR1I

Interrupt on MR1

0 (INTERRUPT_IS_DISABLE): Interrupt is disabled.

1 (INTERRUPT_IS_GENERAT): Interrupt is generated when MR1 matches the value in the TC.
MR1R

Reset on MR1

0 (FEATURE_DISABLED_): Feature disabled.

1 (TC_WILL_BE_RESET_IF_): TC will be reset if MR1 matches it.
MR1S

Stop on MR1

0 (FEATURE_DISABLED_): Feature disabled.

1 (TC_AND_PC_WILL_BE_ST): TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
MR2I

Interrupt on MR2

0 (INTERRUPT_IS_DISABLE): Interrupt is disabled

1 (INTERRUPT_IS_GENERAT): Interrupt is generated when MR2 matches the value in the TC.
MR2R

Reset on MR2

0 (FEATURE_DISABLED_): Feature disabled.

1 (TC_WILL_BE_RESET_IF_): TC will be reset if MR2 matches it.
MR2S

Stop on MR2.

0 (FEATURE_DISABLED_): Feature disabled.

1 (TC_AND_PC_WILL_BE_ST): TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC
MR3I

Interrupt on MR3

0 (THIS_INTERRUPT_IS_DI): This interrupt is disabled

1 (INTERRUPT_IS_GENERAT): Interrupt is generated when MR3 matches the value in the TC.
MR3R

Reset on MR3

0 (FEATURE_DISABLED_): Feature disabled.

1 (TC_WILL_BE_RESET_IF_): TC will be reset if MR3 matches it.
MR3S

Stop on MR3

0 (FEATURE_DISABLED_): Feature disabled.

1 (TC_AND_PC_WILL_BE_ST): TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data